1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a lead-on-chip structure.
2. Description of Related Art
A semiconductor device having a lead-on-chip structure (called a "LOC structure" hereinafter) generally has an inner lead stuck through an adhesive tape on a semiconductor chip, as disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-5-029528, the content of which is incorporated by reference in its entirety into this application (an English abstract of JP-A-5-029528 is available from the Japanese Patent Office, and the content of the English abstract of JP-A-5-029528 is also incorporated by reference in its entirety into this application).
Referring to FIG. 1, there is shown a partially broken, diagrammatic perspective view of the prior art LOC structure semiconductor device disclosed by JP-A-5-029528. FIG. 2 is an enlarged diagrammatic partial sectional view of the prior art LOC structure semiconductor device shown in FIG. 1 and also shown in JP-A-5-029528. FIG. 3A is a further enlarged diagramrnatic partial sectional view of the prior art LOC structure semiconductor device shown in FIG. 1, showing an inner lead stuck on a semiconductor chip, and FIG. 3B is an enlarged diagrammatic partial plan view of the prior art LOC structure semiconductor device shown in FIG. 1, showing an inner lead stuck on a semiconductor chip in a portion shown in FIG. 3A.
The shown LSI packaae is generally designated with Reference Numeral 10, and includes a package body 12 formed of an epoxy resin. In the epoxy resin package body 12, a semiconductor chip 14 is encapsulated. A principal surface 14A of this semiconductor chip 14 is stuck to an insulative adhesive tape 16 to a lower surface of inner leads 18 which are integral with corresponding outer leads 20 (lead frame) extending outwardly from the package body 12- Each inner lead 18 is connected through a bonding wire 22 to a corresponding electrode pad 24 of the semiconductor chip 14. The adhesive tape 16 is constituted of a so called "pressure sensitive adhesive double coated tape". More specifically, the adhesive tape 16 is a polyimide double coated tape, which is as relatively thick as for example 0.1 mm, since the adhesive tape 16 has not only a function of sticking the inner leads to the semiconductor chip but also a function of fixing the inner leads relative to one another in the lead frame before the inner leads are stuck to the semiconductor chip.
In the above mentioned prior art LOC structure semiconductor device, since the adhesive tape 16 exists between the principal surface of the semiconductor chip 14 and a wire bonding portion of each inner lead, the wire bonding portion of each inner lead does not directly contact with the principal surface of the semiconductor chip 14, and on the other hand, the relatively thick adhesive tape 16 acts as a buffer member. When the bonding wire is bonding to the wire bonding portion of the inner lead, a heat and/or an ultrasonic wave applied for the wiling bonding is difficult to conduct or transfer, with the result that the bonding property of the bonding wire to the inner lead is often not satisfactory.